1. Field
The present disclosure relates generally to a three-dimensional semiconductor device and, more particularly, to a three-dimensional semiconductor device including a plurality of U-shaped strings and a manufacturing method thereof.
2. Description of the Related Art
Semiconductor devices having a three-dimensional (3-D) structure (hereinafter referred to also as a 3-D semiconductor device) in which memory cells are 3-Dly arranged have been proposed for increasing integration of the semiconductor devices. Generally, 3-D semiconductor devices utilize the available area of a substrate more efficiently than semiconductor devices having a two-dimensional structure, hence, the integration of 3-D semiconductor devices is higher than the integration of 2-D semiconductor devices. Also, attempts to apply to the 3-D structure a regular arrangement of memory cells in a NAND flash memory device have being made.
Typically, a 3-D semiconductor device may include a string including a plurality of memory cells stacked in a multi-layer structure over a substrate and a select transistor. A string included in a 3-D nonvolatile memory device may have an ‘I’ or ‘U’ shape. A 3-D semiconductor device having an I-shaped string is referred to as terabit cell array transistor (TCAT) or bit-cost scalable (BICS). A 3-D semiconductor device having a U-shaped string is referred to as pipe-shaped, bit-cost scalable (P-BICS).
In a P-BICS, a string may include a pipe transistor and two vertical plugs. The pipe transistor is formed in parallel to a substrate. One vertical plug may be formed in a source region of the pipe transistor, whereas the other vertical plug may be formed in a drain region of the pipe transistor. A source line is formed over the vertical plug formed in the source region, and a bit line is formed over the vertical plug formed in the drain region.